While the majority of mobile customers currently use 4G or 4G LTE networks, the anticipation for 5G service is already making waves through the mobile service and wireless tech industries. Granted we still have at least a year or so from reaping the benefits of 5G, the shift of focus upon this network just goes to show how quickly American consumers are willing to move onto the newest and next big brand or event. In similar fashion, mobile carriers and consumers quickly committed to the newer, faster, more efficient data network, while vacating its 3G predecessor.
While 3G is still somewhat relevant and even used in some cases for actions like voice calls , its days do appear to be numbered. With millions of mobile wireless users on the 4G and 4G LTE networks in the United States, its 3G predecessor is experiencing the same signs of long-term uncertainty that 2G endured.
One of the main factors behind the seemingly inevitable demise of 3G service in the United States are the different approaches major carriers took when transitioning from 3G to 4G and LTE. As a result, manufacturers developing new devices for American carriers are given practically little to no choice other than supporting frequencies for LTE operations. Other major carriers like Verizon announced they will discontinue support for 3G devices on their network by the end of Note: If you are using a browser that is not listed here, please do a quick internet search on how to block cookies and tracking for your specific browser.
This means that complex embedded memory solutions become available almost a year after the standard CMOS implementation. SiP offers one cost-effective solution to the embedded memory dilemma. The stacked die SiP implementation provides the same small footprint as a SoC solution.
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In this implementation one or more commodity memory die is stacked on top of the SoC logic device. Low-cost wirebond assembly technology interconnects the devices, which are encapsulated in an inexpensive chip-sized ball-grid array BGA package Fig.
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Because the stacked die approach doesn't add process complexity to the high-performance CMOS communications processor, but leverages cost-effective commodity memory, it offers the best of both worlds. It doesn't normally require custom chips, which helps reduce time to market. And, because it adds space vertically, rather than horizontally, it fits the footprint suitable for battery-operated consumer products. Analog and power-management integration Today, analog and power management functions are normally implemented in analog process technologies, very different from the deep submicron CMOS used for digital baseband chips.
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If the analog and power-management functions can be implemented in deep submicron digital CMOS without adding process complexity, then the SoC integration of analog and power management functions can be a low-cost approach. The biggest challenge in implementing high-speed and high-precision analog functions in digital CMOS is the process' low power supply voltage. Because of these limitations, it usually isn't feasible to copy existing analog functions in digital CMOS.
Instead, the total system must be re-optimized to take advantage of digital CMOS and to develop new architectures to exploit the benefits of low-voltage and low-cost digital logic. In most cases, these architectures are well-known, but the low-voltage trade-offs are different:. In an example of a re-optimized design, the bit delta- sigma ADC takes advantage of the logic and high-speed switching capability of 90nm CMOS.
Such a converter's high resolution and sampling rate allow more of the radio-channel signal processing to be done in the digital domain. This digital processing improves flexibility and reduces cost and power versus a more heavily analog implementation. Power management is becoming increasingly distributed, especially in low-power applications, because of the need to reduce standby power by putting unused logic and memory in a standby or sleep mode.
Much of this power management functionality can be accomplished using switches to activate or deactivate logic blocks. In addition, local, on-chip voltage regulation is also needed, and this requires on-chip low-drop out LDO regulators. DE CMOS can also be used to implement high-voltage battery charger circuitry in battery-operated products. Over the past several years, tremendous progress had been made in implementing analog and power management functions in deep submicron CMOS.
Today, many analog functions required in a cellular handset can be implemented cost effectively in deep submicron digital CMOS. Consequently, SoC integration, coupled with the DBB chip, offers an attractive path to combined analog and power-management circuitry. Radio integration The radio in a modern handset faces some severe performance requirements.
Signals with amplitudes of only a few microvolts must be received in the face of strong interferers, high output power levels roughly 30 dBm must be produced to drive the antenna, and isolation between various radios within the handset must be accounted for. In addition, radio designs require accurate filtering at high frequencies and good matching between circuits in the signal path.
These combined requirements make radio integration a considerable challenge and make the choice of SiP vs.
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SoC for the radio function a complex decision. Looking at the typical functions found in a modern GSM radio, the transceiver contains the small-signal radio electronics needed for up- and down-converting the information signal to the transmission band Fig. The power amplifier PA module amplifies the transceiver output to produce an output signal with adequate power for reliable transmission. The front-end FE module normally includes the RF switch function for separating the time-multiplexed transmit and receive signals and the RF preselect filters which are normally surface acoustic wave SAW devices the module can be partitioned in other ways, as well.
A similar diagram would represent a cellular standard, such as CDMA, that implements full-duplex operation in the air interface. However, the switch function would be replaced by a duplexer. One possible partitioning option for the radio electronics, an SoC, integrates the radio transceiver with the baseband processor. Alternatively, using SiP integration, the transceiver could be integrated with the PA and FE modules to create one analog radio module.
Because interfacing the radio signals between analog functions normally requires matching networks, many passive components are associated with the radio design. Consequently, it's advantageous to pull as many passive elements as possible into the PA and FE modules.
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However, some designs integrate the entire radio function into one package. Ultimately, a discussion of SiP vs. Because SiP allows use of a conventional analog RF transceiver, no new transceiver architectures or special IC technology is required. The transceiver capability is well established and, apart from layout considerations associated with module integration bond pad placement, IC aspect ratios, etc. However, integrating the transceiver also offers little in terms of improving the overall system. While board area may be reduced, no improvement in power consumption is gained and the overall system cost may increase.
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SoC integration of the transceiver is normally undertaken with monolithic integration in deep submicron CMOS. However, the additional reticles required for a SiGe wafer would drive up the cost of the system logic and memory, and the lack of SiGe processes at state of the art lithography would increase the logic area. Also, the benefits associated with tightly coupling the system logic with the radio function wouldn't be fully realized if a conventional radio is employed. Fortunately, deep submicron CMOS transistors offer good RF performance and meet the needs of integrated transceiver designs low noise figures and high transition frequencies are possible.
However, conventional RF transceiver designs make extensive use of analog components and require high-performance passive elements.
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Producing such a design in CMOS would normally require several additional processing steps to produce the resistors, capacitors, and inductors needed. Given the tremendous logic density and high clock speeds offered by deep submicron logic processes, however, it seems natural to look for ways to exploit this process technology through SoC. Doing so may require developing new radio architectures for implementation in deep submicron CMOS, but it can provide significant advantages.
Foremost among them is the fact that, as advances in CMOS wafer processing produce faster switching speeds, it becomes possible to sample at higher rates.
Oversampling of the input signal reduces noise aliasing problems and relaxes the input networks design.
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